In clocked memory systems, data is transmitted along with an accompanying timing reference signal in both directions over a channel. This timing reference signal (or timing signal) can be a clock signal, a strobe signal, or another form of timing reference signal. For example, some memory systems utilize a timing reference signal to provide source synchronous clocking events for data signals associated with read and write accesses. Unfortunately, as the signaling rate increases, it becomes challenging to synchronize these signals properly.
In particular, the total communication path length through memory system components is often relatively long. For example, the read path includes circuitry for generating the read command in the clock domain of a memory controller, circuitry for transmitting this information between the memory controller and a memory device, circuitry for receiving the information at the memory device, circuitry for accessing the read data from the memory core, circuitry for transmitting the read data and a corresponding timing reference signal to the memory controller, and circuitry for receiving the read data using the timing reference signal at the memory controller. This communication path includes various delays that may change as operating conditions, such as temperature or a supply voltage, vary. By the time the read data and the associated timing reference signal are received at the memory controller, the phase relationship between the controller's clock domain and the returned timing reference signal may be uncertain.